1. Field of the Invention
This invention relates to a maximum likelihood decoding technique which, for example, is suitable for application to a videotape recorder or optical disk device.
2. Description of the Related Art
In the prior art, in videotape recorders and optical disk devices, digital signals which are recorded at high density are faithfully reproduced by processing reproduced signals by Viterbi decoding.
In Viterbi decoding, input data is processed by defining n types of state, determined by intercode interference, by a combination of immediately preceding input data, and updating these n types of state to the following n types of state each time the input data changes. Specifically, if the intercode interference length is m, these n states are determined by the immediately preceding m-1 bits, e.g., if the input data is logic 1 or logic 0 serial data, there are n=2(m-1) states.
Concerning the n states so defined, assuming that the noise contained in the reproduced signal is a Gaussian distribution and taking the value of the reproduced signal corresponding to each state when there is no noise present as a reference amplitude value, the likelihood or probability of making a transition to each state is a value obtained by raising the difference between the reference amplitude value and the actual reproduced signal to a power of two (which is the distance from the reference amplitude value), and summing this square value until there is a transition to each state. In this way, in Viterbi decoding, sums are calculated respectively for paths via which transitions from the immediately preceding n states to the following states are possible, and assuming that transitions occur for paths which have the highest likelihood (smallest sum value) from the calculated results, the n states are updated to the following n states, and the history and likelihood of the identification values in each state are also updated.
By successively detecting the most likely state transitions in this way, the history up to plural preceding bits are merged into one history at a predetermined stage, and the identification result up to that time is thereby specified. This is how Viterbi decoding identifies a reproduced signal.
In Viterbi decoding which processes reproduced signals in this way, if the noise superimposed on the reproduced signal is random noise, maximum use is made of the signal power of the reproduced signal to identify the reproduced signal, and this permits improvement of the error rate as compared with the decoding method where the reproduced signal is decoded by comparing it with a predetermined threshold value for each bit.
FIG. 14 is a table showing state transitions in an EPR (Extended Partial Response) 4 equalization for a recorded signal which allows a logic level inversion for one clock interval in a continuous serial bit sequence, i.e., for a recorded signal wherein d is not limited. The EPR4 is PR(1, 1, xe2x88x921, xe2x88x921), and intercede interference occurs up to three bits later relative to one input data.
Therefore in this combination, the state transition (output) due to the following input data is uniquely determined by the history of input data up to three previous bits. Herein, a[k] represents the input data, and a[kxe2x88x921], a[kxe2x88x922], a[kxe2x88x923] are respectively input data one clock, two clocks and three clocks prior to the input data a[k]. A state b[kxe2x88x921] due to this input data a[kxe2x88x921], a[kxe2x88x922], a[kxe2x88x923] is shown by the values of a code S and the input data a[kxe2x88x921], a[kxe2x88x922], a[kxe2x88x923]. In this case, in a state (S000) for example, if an input a[k] of value 0 is input, an output c[k] of value 0 is obtained, and the state b[k] changes to (S000).
In this case, as there is no limit d=1, 8 states (S000)-(S111) are obtained corresponding to combinations of three successive input data, and the output signal c[k] has five reference amplitude values xe2x88x922, xe2x88x921, 0, 1, 2. If these relations are represented by a trellis diagram, they appear as shown in FIG. 15.
In this case, in Viterbi decoding, from a trellis diagram drawn by repeating FIG. 15, the branch metric of the difference between the reproduced signal and the reference amplitude value is summed, and the path having the least value of this sum is selected to decode the input signal.
FIG. 16 is a block diagram showing a reproduction device to which this type of Viterbi decoder is applied. In a reproduction device 1, a reproduction equalizer 2 performs Nyquist equalization and outputs a reproduction signal RF to permit reproduction of a clock by the reproduction signal RF. A binarizing circuit 3 binarizes the equalized signal output by this reproduction equalizer 2 so as to output a binarized signal S2.
A PLL circuit 4 which operates based on this binarized signal S2 as a reference, reproduces and outputs a clock CK from the reproduction signal RF. An analog/digital (A/D) conversion circuit 5 sequentially performs analog/digital conversion on the reproduction signal RF based on this clock CK, and outputs a digital reproduced signal. By performing computational processing on this digital reproduced signal, a reproduction equalizer 6 generates and outputs an EPR4 equalized signal, for example, and a Viterbi decoder 7 processes the EPR4 equalized signal from this reproduction equalizer 6 to output a binary decoded output D1 which is a recorded signal recorded on a recording medium. Hence, this reproduction device 1 uses the technique of PRML (Partial Response Maximum Likelihood) to reproduce the binary decoded output D1.
FIG. 17 is a block diagram showing this Viterbi decoder 7. In this Viterbi decoder 7, a branch metric calculator 7A receives a digital reproduction signal DRF due to the EPR4 equalized signal, and by performing the following computational processing on each sample value of the digital reproduction signal DRF, calculates and outputs branch metrics BM0[k]-BM4[k] relative to reference amplitude values. Herein, the branch metrics BM0[k]-BM4[k] are differences between values of the reproduced signal corresponding to each state when no noise is present (reference amplitude values which in this case are the five values 2, 1, 0, xe2x88x921, xe2x88x922) and a real reproduced signal level Z[k] raised to the power of 2, and are Euclidian distances of the reproduced signal level relative to the reference amplitude values.
BM0[k]=(Z[k]xe2x88x922)2
BM1[k]=(Z[k]xe2x88x921)2
BM2[k]=(Z[k])2 
BM3[k]=(Z[k]+1)2
BM4[k]=(Z[k]+2)2xe2x80x83xe2x80x83(1)
Specifically, the branch metric calculator 7A comprises plural subtractor circuits which compute the reference amplitude values from the digital reproduction signal DRF, and plural multiplier circuits which raise the subtraction results to the power of 2.
A branch metric processing circuit 7B performs the computations of the following equations respectively in metric calculators 7BA-7BH using the branch metrics BM0[k]-BM4[k] output by the branch metric calculator 7A, and thereby calculates the metrics (S000, k)-(S111, k) which are sum values of the branch metrics input to each state. Herein, min{a, b} is processing which selects the least value of a, b.
L(S000, k)=min {1(S000, kxe2x88x921)+BM2[k], (S100, kxe2x88x921)+BM3[k]}xe2x80x83xe2x80x83(2-1)
L(S001, k)=min {1(S000, kxe2x88x921)+BM1[k], (S100, kxe2x88x921)+BM2[k]}xe2x80x83xe2x80x83(2-2)
L(S010, k)=min {1(S001, kxe2x88x921)+BM1[k], (S101, kxe2x88x921)+BM2[k]}xe2x80x83xe2x80x83(2-3)
L(S011, k)=min {1(S001, kxe2x88x921)+BM3[k], (S101, kxe2x88x921)+BM1[k]}xe2x80x83xe2x80x83(2-4)
L(S100, k)=min {1(S010, kxe2x88x921)+BM3[k], (S110, kxe2x88x921)+BM4[k]}xe2x80x83xe2x80x83(2-5)
L(S101, k)=min {1(S010, kxe2x88x921)+BM2[k], (S110, kxe2x88x921)+BM3[k]}xe2x80x83xe2x80x83(2-6)
L(S110, k)=min {1(S011, kxe2x88x921)+BM2[k], (S111, kxe2x88x921)+BM3[k]}xe2x80x83xe2x80x83(2-7)
L(S111, k)=min {1(S011, kxe2x88x921)+BM1[k], (S111, kxe2x88x921)+BM2[k]}xe2x80x83xe2x80x83(2-8)
The branch metric processing circuit 7B also outputs determining results SEL0-7 due to the metric calculators 7BAxe2x80x947BH.
FIG. 18 is a block diagram showing the detailed construction of the branch metric calculator 7B. In the branch metric calculator 7B, the metric calculators 7BA-7BF have an identical circuit layout excepting that the inputs/outputs are set corresponding to the state transitions shown in FIG. 15, therefore here only the metric calculator 7BA corresponding to the state S000 will be described and identical parts of the description will be omitted.
Specifically, in the calculator 7BA which calculates a metric for the transition to the state (S000), an adder circuit 10 adds the metric L(S000, kxe2x88x921) of the state (S000) calculated one clock previously in this first metric calculator 7BA, and the branch metric BM2[k] calculated by the branch metric calculator 7A, and outputs the result. Thus, the adder circuit 10 outputs an addition result corresponding to the first term on the right-hand side of equation (2-1).
An adder circuit 11 adds the metric L(S100, kxe2x88x921) of the state (S100) calculated one clock previously in the fifth metric calculator 7BE, and the branch metric BMB3[k] calculated by the branch metric calculator 7A, and outputs the result. Thus, the adder circuit 11 outputs an addition result corresponding to the second term on the right-hand side of equation (2-1).
A comparator circuit 12 outputs the result of comparing output data from the adder circuits 10 and 11. Thus, the comparator circuit 12 determines from which of the states (S000) and (S100) a transition to the state (S000) is most likely (probable), and outputs this determining result SEL0.
A selector 13 selects and outputs the addition result of the adder circuits 10, 11 according to the determining result SEL0 of the comparator circuit 12, and thereby outputs the computational processing result on the right-hand side of equation (2-1). A latch (D)14 delays the computational processing result by one clock period by latching the selection output of this selector 13, after which it is output.
A path memory unit 7C (FIG. 17) generates the binary decoded output D1 by processing the calculation results of the branch metric calculator 7B respectively by path memories 7CA-7CH, and outputs the result.
FIG. 19 and FIG. 20 are block diagrams showing part of the path memory unit 7C. In FIG. 19, the path memory 7CA comprises a predetermined number of latches (number of latches equal to or greater than the number of merging paths, generally a number of latches equivalent to 16 to 32 bits) 16A-16N connected in series, and selectors 17A-17M which selectively output the history of the fifth path memory 7CE or the history of the immediately preceding latch, are disposed between these latches 16A-16N.
These selectors 17A-17M change over operation according to the determining result SEL0. In this way, in the corresponding metric calculator 7BA, if the metric from the fifth state (S100) is selected, the history of the path memory 7CE is selected and output. On the other hand, if the metric from the first state (S000) is selected, a self-history held in the immediately preceding latch is selected and output. The first latch 16A latches corresponding fixed data of value 0 for both of these transitions, and the last latch 16N outputs the binary decoded output D1.
The path memory 7CH of the eighth state (S111) is identical to the first path memory 7CA excepting that in the construction shown in FIG. 19, the history of the fourth path memory 7CD is selectively received instead of the history of the fifth path memory 7CE, fixed data of value 1 is latched by the first latch 16A instead of the fixed data of value 0 corresponding to the received history, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
On the other hand, the second path memory 7CB (FIG. 20) comprises the latches 16A-16N of identical number to those of the path memory 7CC, and the selectors 17A-17M which selectively output the history of the first path memory 7CA or the history of the fifth path memory 7CE, disposed between the latches 16B-16N excluding the first latch 16A.
These selectors 17A-17M change over operation according to the determining result SEL1, and consequently in the corresponding metric calculator 7BB, if the metric from the first state (S000) is selected, the history of the path memory 7CA is selected an output. On the other hand, if the metric from the fifth state (SL00S) is selected, the history of the path memory 7CE is selected and output. The first latch 16A latches corresponding fixed data of value 1 for both of these transitions. The last latch 16N outputs the binary decoded output D1.
The path memory 7CC of the third state (S010) is identical to the second path memory 7CB excepting that in the construction shown in FIG. 20, the history of the second or sixth path memory 7CB is selectively received instead of the history of the first or fifth path memory 7CA or 7CE, fixed data of value 0 is latched by the first latch 16A instead of the fixed data of value 1 corresponding to the received history, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
The path memory 7CD of the fourth state (S011) is identical to the second path memory 7CB excepting that in the construction shown in FIG. 20, the history of the second or sixth path memory 7CB or 7CF is selectively received instead of the history of the first or fifth path memory 7CA or 7CE, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
The path memory 7CE of the fifth state (S100) is identical to the second path memory 7BA excepting that in the construction shown in FIG. 20, the history of the third or seventh path memory 7CC or 7CD is selectively received instead of the history of the first or fifth path memory 7CA or 7CE, fixed data of value 0 is latched by the first latch 16A instead of the fixed data of value 1 corresponding to the received history, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
The path memory 7CF of the sixth state (S101) is identical to the second path memory 7CB excepting that in the construction shown in FIG. 20, the history of the third or seventh path memory 7CC or 7CG is selectively received instead of the history of the first or fifth path memory 7A or 7CE, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
The path memory 7CG of the seventh state (S110) is identical to the second path memory 7CB excepting that in the construction shown in FIG. 20, the history of the fourth or eighth path memory 7CD or 7CH is selectively received instead of the history of the first or fifth path memory 7CA or 7CE, fixed data of value 0 is latched by the first latch 16A instead of the fixed data of value 1 corresponding to the received history, the destination to which the history is sent is different, and the change-over signal of the selectors 17A-17M is different.
Due to these constructions, when the path memories 7CA-7CH receive a history of a predetermined number of stages, an identical history is held in the corresponding latch. In the Viterbi decoder 7, the binary decoded output D1 is therefore obtained from the last latch 16N of any of the path memories 7CA-7CG.
However, in this type of recording and reproduction system, the ability to identify reproduced data can be enhanced by increasing the intercode interference length m. As described above, the number of states S due to the intercede interference length m can be represented by 2(m-1), therefore the number of states increases in terms of indices and parameters when the intercede interference length m is increased. On the other hand in the Viterbi decoder 7 of the prior art, the same number of metric calculators 7BA-7BH and path memories 7CA-7CH as the number of states is required, and when the number of states increases, the construction becomes exceedingly complex.
In this type of recording and reproduction system, an intercede interference length m of a certain length had to be tolerated due to the scale of the circuit.
It is therefore an object of this invention, which was conceived in view of the above problems, to provide a data decoding apparatus and data decoding method which can realize maximum likelihood decoding by a simple construction.
To resolve the above problems, in the data decoding apparatus or data decoding method according to this invention, a logic level inversion timing during one clock interval is detected from an input signal, a provisional identification result of identifying the input signal is corrected by effectively one clock identification error, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result.
Further, in the data decoding apparatus or data decoding method according to this invention, a provisional identification result is obtained by identifying an input signal by effectively one clock identification error, a logic level inversion interval is corrected when a logic level inversion interval occurs in a shorter interval than a permitted logic level inversion interval in the input signal, the number of state transitions which can be obtained from the input signal is limited based on this corrected provisional identification result, and the most probable state transition of these limited state transitions is detected to output an input signal identification result.